The integration of heterogeneous components using 3D technologies is crucial for future system scaling, especially in high-performance, low-power systems where computing and memory functions are optimized and integrated.
Within the PREVAIL framework, the RTOs (IMEC, CEA-LETI, FhG) are developing new 3D technology flows for edge AI applications, leveraging their existing and expanded technological capabilities to propose new combined 3D offerings, such as Si Interposers with front- and backside RDL, mixed pitch interconnect formation, Die-to-Wafer assembly, TSV formation and/or singulation.
The three RTOs offer a broad portfolio of 3D 300 mm Si wafer technologies, enabling the integration of dedicated building blocks into edge AI systems, which significantly enhance system performance and integration density. Additionally, VTT provides building blocks for smaller wafer sizes (200 mm and below) to support 3D integration on those sizes.
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Through-Silicon Via (TSV) technology addresses the limitations of traditional two-dimensional integrated circuits (2D ICs) by creating vertical electrical connections between the front and back sides of silicon wafers or dies. This allows for the interconnection of multiple chips, memory, sensors, and other modules, resulting in smaller, faster, and more power-efficient devices.
Key Advantages of TSVs:
Reduced Signal Propagation Delay: Data signals travel vertically through the thinner silicon substrate, significantly reducing signal propagation delay.
Lower Power Consumption and Area: Shorter interconnect lengths reduce the overall area and power consumption of the chip, making TSVs ideal for high-speed applications such as data centers, servers, GPUs, AI-based processors, and wireless communication devices.
• Heterogeneous Integration: TSVs enable the combination of multiple chips from different technologies and manufacturers, facilitating heterogeneous integration.
The PREVAIL TEF will offer TSV solutions that are fully integrated with CMOS technologies, enhancing the performance and efficiency of various high- speed applications.
The choice of TSV technology depends on the final application, but usually a combination of technologies is used. Our offer will start with:
Via Middle
In this type of technology, TSVs are created after the active circuitry is fabricated on the wafer but before the fabrication of metallization layers (BEOL, i.e., the back end of the line). This Via Middle approach is primarily used to connect both the active and passive layers of the integrated circuits through TSVs. This approach is mainly used in applications such as microprocessors and memory devices.
Via Last
In this type of technology, TSVs are fabricated after the fabrication of active layers, i.e., FEOL, and after (or during) the metallization layers, i.e., BEOL. This Via Last approach connects the TSVs to the external package or substrate through a metal redistribution layer (RDL) and an interconnections like Cu pillars or solder bumps. This approach is often used in microelectronic systems.
TSVs last with aspect ratios of 2 and 5, respectively
Advanced 2.5D, 3D and heterogeneous die stacking technologies require increasingly denser interconnects with reduced die separation, improved thermal performance, and high current carrying capabilities.
Within PREVAIL TEF, different types of fine pitch interconnects will be offered:
• Die-to-Wafer Bonding Using Microbumps
The state-of-the-art microbump pitches in production have saturated at about 30μm. Using material innovations, interconnect pitches down to 7μm could be demonstrated. Such high-density connections leverage the full potential of Through- Silicon Via technology, enabling more than 16 times higher 3D interconnect densities.
Figures courtesy of imec
• Die-to-Wafer Bonding Using Hybrid Bonding Solutions
Hybrid bonding solutions with pitches down to 3μm are possible in this case. Hybrid bonding allows for very high interconnection densities, ranging from (10^4) to (10^6) interconnections per mm2. The die-to-wafer approach is more flexible and cost-effective compared to the classical wafer-to-wafer approach. This method allows the use of Known Good Dies (KGD) to improve the final yield of the assembly and enables the integration of chips from different sources. Another advantage is the ability to reduce the inter-die spacing to a few microns for the chip matrix assembly.
P. Metzger et al., Minapad forum 2022
• High precision chip bonding
IC-Systems for advanced AI applications and high-performance computing architecture typically require a high number of interconnects (I/O) between 3D-stacked ICs. This requires smaller pad sizes and pad distances, both down to 1 µm. Consequently, adequate equipment for die assembly must be capable of aligning and place ICs on wafers or dies at an accuracy below 0.5 µm. Furthermore, this precision must be maintained for temperature-assisted bonding techniques, such as soldering by means of micro bumps.
High-precision chip bonding equipment capable to fulfil these requirements will be installed at the PREVAIL partners’ laboratories starting mid-2025.
Current precision chip assembly for new IC systems © Fraunhofer EMFT
3D-integration methods are often based on interposer technologies. Until today, silicon or glass wafers have been dominantly used as substrate materials for such interposers. Extending interposer technologies to polymeric film substrates opens the door to new types of 3D-stacking architectures.
The physical properties of flexible films facilitate the compensation of topography and related height differences in stacked IC configurations. Specific advantages of films, such as Polyimide (PI), include a very smooth surface and low dielectric constant. Both allow for high-performance electrical interconnects on film strips, to be used as data links between ICs placed at different levels of adjacent die stacks.
Chip-to-Foil assembly © Fraunhofer EMFT
Furthermore, assembly technologies for single dies on film substrates enable new packaging concepts, such as embedding of the IC in cavities or flip-chip bonding with subsequent rear-side encapsulation. In particular, thinned micro-processors can be embedded in super-thin film packages, resulting in packaged IC devices with a thickness below 150µm.
Such innovative chip packages would support edge AI applications for sensors that need to be attached to the human body, for example.
Micro-processor IC in thin film package, lab demonstrator © Fraunhofer EMFT / Bernd Müller
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PREVAIL project partners
PREVAIL
A multi-hub Test and Experimentation Facility for edge AI hardware
Grant Agreement No. 101083307