DEMONSTRATORS
Demostrators will serve as pipe cleaners for our technologies
Demonstrators will serve as pipe cleaners for our technologies, providing a glimpse of PREVAIL TEF capabilities.
The first demonstrator will contain two key technologies, AI and NVMs.
Here, an AI-accelerator and a MRAM high-level cache memory will be connected through a FPGA platform that will be controlling the data acquisition and data flow. As specific use-case, smart camera inputs will be analyzed with MRAM chips acting as video history buffer.
News of the status of the demonstrators will be shared during Q4/2024-Q1/2025.
eNVM demonstrator
This first demonstrator will contain two key technologies, AI and N VMs.
Here, an AI-accelerator and a MRAM high-level cache memory will be connected through a FPGA platform that will be controlling the data acquisition and data flow. As specific use-case, smart camera inputs will be analyzed with MRAM chips acting as video history buffer.
STT-MRAM process flow
Combination of an AI-accelerator and a MRAM memory: system level view of a planned demonstrator for image processing use-case.
Silicon Photonics demonstrator
The silicon photonics demonstrator combines the strength of IMEC and LETI’s advanced photonics integration. IMEC’s active silicon photonics platform, blending high-quality active and passive components, is combined with backside evanescent coupling developed by LETI to enable heterogeneous integration or multi-level photonics circuits. It is the latter enablement that will be pursued through a photonic circuit to realize a vector matrix product that requires low-loss silicon crossings.
The photonic circuit* will be composed of three parts:
• an input stage where Mach-Zehnder modulators operating at high speed (10GHz or more) will convert the input data stream to the optical domain.
• a computing stage where the input optical waves will be mixed and weighted to form the results of the computation.
• an output stage with integrated photodetectors where the resulting optical waves are converted back to the electrical domain, ready for conversion to the digital domain.
The resulting operation will lead to vector-matrix products performing at 10GHz+ rates. *Photonic circuit is currently at the design stage.
3D-Integration demonstrator
PREVAIL project partners
PREVAIL
A multi-hub Test and Experimentation Facility for edge AI hardware
Grant Agreement No. 101083307